Semiconductor devices

ABSTRACT

A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. application Ser.No. 11/138,298, filed May 27, 2005, and which said application claimspriority from Japanese Patent Application 2004-272955, filed Sep. 21,2004, the entire contents of which are hereby incorporated by referenceinto this application.

BACKGROUND OF THE INVENTION

The present invention relates to semiconductor devices, and moreparticularly to the structure of silicon carbide semiconductor deviceswhich include vertical field effect transistors.

Silicon carbide (SiC) has a breakdown electric field approximately tentimes larger than silicon (Si), so that when it is used for verticalfield effect transistors, a drift layer (epitaxial layer) formaintaining the breakdown can be made thin and highly dense to reduce aloss. SiC-based power semiconductor devices include a junction FET(JFET) and a static induction transistor (SIT).

JP-A-9-508492 (FIGS. 6 to 11), Materials Science Forum Vols. 433-436(2003), pp. 777-780, and IEEE ELECTRON DEVICE LETTERS VOL. 24, NO. 7,JULY 2003, pp. 463-465 disclose semiconductor devices which utilizeadvantages of silicon carbide (SiC). In these documents, an n⁺ substratewhich defines a drain region, and an n⁻ epi-layer are formed from onesurface side of a silicon carbide semiconductor substrate, while an n+source region is formed on an n-type epi-layer. Here, deep trenchgrooves are dug into an n-type epi-layer, and a p⁺ gate region is formedalong the grooves. This p⁺ gate region extends to a position at which itcomes into contact with the n⁺ source region. Between adjacent trenchgrooves, a source electrode is formed on the surface of the n⁺ sourceregion, which extends along the other side, through a source contactlayer which is in contact with the n⁺ source region. This sourceelectrode is formed across the whole length of the semiconductorsubstrate on the opposite surface thereof in all directions, astride notonly the surface of the n⁺ source region but also the surface of aninsulating material in the trench grooves. On the other hand, a gatecontact layer is disposed on the bottom of the trench grooves forconnection with the p⁺ gate region. These JFET and SIT are transistorswhich turn on and off a current with a depletion layer which extendsover a channel in the p⁺ gate region between a pair of adjacent trenchgrooves. By miniaturizing the width of this channel, a so-called“normally-off” type transistor is achieved for holding an off state evenwhen a gate voltage is zero.

Materials Science Forum Vols. 433-436 (2003) pp. 777-780 discloses thata breakdown voltage as high as 650 volts and a forward current densityas high as 250 A/cm² can be accomplished by choosing the concentrationof an n-type epi-layer, which serves as a drift layer, to be 3E15/cm⁻³,and a gate voltage Vg equal to zero volt, with a channel width of 2.0 μmand a groove width of 2.0 μm.

On the other hand, calculations made by the present inventors haverevealed that a forward current density as high as 400 A/cm², evenexceeding that possible with silicon insulated gate bipolar transistor(IGBT) can be accomplished by increasing an impurity concentration of anepi-layer to 2E16/cm⁻³, and choosing a groove width of 1.0 μm (channelwidth of 0.5 μm) and a groove depth of 1.2 μm. However, a narrowergroove width causes difficulties in drawing out a wire through a sidewall for connecting a gate electrode to an external pad because ofpossible disconnection of metal wiring. Also, while a pad electrodecould be formed by an electrically conductive region which extendsthrough a conductive region of the gate area to reach the pad, a largeresistance of the gate area makes it impossible to accomplish atransistor which can perform high speed switching operations.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide semiconductordevices which are capable of increasing the current density andaccomplishing high speed switching operations.

In a preferred embodiment of the present invention, a semiconductordevice such as JFET, SIT or the like includes a gate electrode in ohmiccontact with a gate region, and a metal conductor (virtual gateelectrode) in ohmic contact with the gate region independently of thegate electrode.

Also, in a preferred embodiment of the present invention, asemiconductor device includes a gate electrode in ohmic contact with agate region on a surface of a semiconductor substrate on which a sourceelectrode is disposed, and a metal conductor (virtual gate electrode) inohmic contact with the gate region on the bottom of each trench grooveindependently of the gate electrode.

Further, in another preferred embodiment of the present invention, asemiconductor device includes a gate electrode which is in ohmic contactwith a gate region on the bottom of a first trench groove, and a metalconductor (virtual gate electrode) in ohmic contact with the gate regionon the bottom of a second trench groove.

According to the preferred embodiment of the present invention, thesemiconductor device can have a high current density and reduce the gateresistance with the aid of the metal conductor (virtual gate electrode)in ohmic contact with the gate region to enable high-speed switchingoperations.

Other objects, features and advantages of the invention will becomeapparent from the following description of the embodiments of theinvention taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view generally illustrating the structure ofa static induction transistor (SIT) according to a first embodiment ofthe present invention;

FIG. 2 is a cross-sectional view generally illustrating the structure ofa SIT according to a second embodiment of the present invention;

FIG. 3 is a cross-sectional view generally illustrating the structure ofa SIT according to a third embodiment of the present invention;

FIG. 4 is a cross-sectional view generally illustrating the structure ofa SIT according to a fourth embodiment of the present invention;

FIG. 5 is a cross-sectional view generally illustrating the structure ofa SIT according to a fifth embodiment of the present invention;

FIG. 6 is a cross-sectional view generally illustrating the structure ofa SIT according to a sixth embodiment of the present invention;

FIG. 7 is a cross-sectional view generally illustrating the structure ofa SIT according to a seventh embodiment of the present invention;

FIG. 8 is a top plan view illustrating the layout of a mask pattern forimplementing the first embodiment of the present invention;

FIG. 9 is a top plan view illustrating the layout of another maskpattern for implementing the first embodiment of the present invention;and

FIGS. 10A to 10I are cross-sectional views illustrating the structure ofthe SIT in manufacturing steps A-I for manufacturing the SIT accordingto the first embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

For increasing a blocking effect of a gate, it is effective to narrowdown a channel width. Also, a narrower channel width can increase animpurity concentration of an n⁻ drift layer (epitaxial layer) and reducethe on-resistance of a transistor. However, the narrower channel widthresults in difficulties in routing a metal wire from a gate region belowgrooves through a groove side wall to a region above the grooves. Thisis because the deep grooves cause interruptions of the metal wire. Onthe other hand, it is possible to completely embed a metal CVD (ChemicalVapor Deposition) film in grooves, such as a plug tungsten wire used inLSIs and the like, for routing from the gate region to a region abovethe grooves. However, with JFET and SIT which have a source region abovetrench grooves, complete separation from the source region is required,thus leading to an extremely complicated manufacturing process. It isalso contemplated to connect from a gate diffusion region (gate draw-outlayer) on the bottom of the groove to the surface of the semiconductorsubstrate through a gate region and route a metal wire only on thesurface of the semiconductor substrate. However, an increased resistance(R) of the gate diffusion region, i.e., an increased gate resistance anda gate capacitance (C) result in an increased CR time constant, leadingto the inabilities to perform high speed switching operations.

To overcome the foregoing problems, in some embodiments of the presentinvention, a metal conductor (virtual gate electrode) is formed on thebottom of grooves in ohmic contact with a gate region, in addition to agate electrode. As has been previously discussed, the metal conductorhas difficulties in electric connection with the gate electrode and isinsulated from the gate electrode, but is effective for reducing thegate resistance to accomplish high speed switching operations for JFETand SIT. Specifically, since an ohmic contact is formed between themetal conductor (virtual gate electrode) and the gate electrode on thebottom of the groove, the gate resistance is significantly reduced, ascompared with a structure which does not have such a metal conductor.

Also, in silicon carbide (SiC), either a laminated film made of titaniumand aluminum or a nickel film is generally used for a metal wire to forman ohmic contact with a p-type region. In either case, after a metalfilm has been formed, the resulting product is treated at hightemperatures of approximately 1,000° C. to form a silicidation filmbetween SiC and metal region, thereby forming an ohmic contact. Also,the titanium/aluminum laminate film has a smaller contact resistancethan the nickel film. However, when the titanium/aluminum laminate filmis thermally treated at approximately 1,000° C., aluminum will melt, sothat the titanium/aluminum laminate film cannot be used in a scale-downpattern.

To address the foregoing problem, in some embodiments of the presentinvention, an oxide film is embedded in the grooves after thetitanium/aluminum laminate film has been formed on the bottom of thegrooves, before a high-temperature heat treatment. In this way, even ifthe titanium/aluminum laminate film melts, it will not diffuse becauseit is covered with the oxide film.

Also, a nickel film is formed above the grooves. The nickel filmprevents the laminate film from melting even in a high temperaturetreatment at 1,000° C., and permits simultaneous formation of a sourceelectrode in ohmic contact with an n-type high concentration sourceregion.

From the foregoing strategies, the gate resistance can be reduced evenin JFET and SIT which have scale-down channel widths, so that high speedswitching operations can be accomplished. For example, when thesemiconductor device according to the present invention is used as ahigh-current switching device for a PWM inverter, the device can bereadily controlled and reduce a loss.

Now, some embodiments of the present invention will be described ingreater detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view illustrating the structure of a staticinduction transistor (SIT) according to a first embodiment of thepresent invention. In FIG. 1, a semiconductor substrate, the band gap ofwhich is 2.0 eV or more, has a substrate 10 of a first conductivity typen⁺ (or p⁺) in a low impurity concentration, which defines a drainregion, and a drain electrode 22 formed over the entirety of one surfaceof the substrate 10. An epitaxial layer (drift layer) 11 is formed onthe opposite surface of the substrate 10. The epitaxial layer 11 has ahigher impurity concentration than the substrate 10 of the firstconductivity type and a low resistance. An n⁺ source region 12 is formedon the opposite surface of the semiconductor substrate. On the surfaceof the source region 12, a source contact layer 21 made of nickel isformed in order to form an ohmic contact. An aluminum-made sourceelectrode 23 is disposed on the source contact layer 21. In thisembodiment, the aluminum-made source electrode 23 is made thick on theassumption that the SIT is applied with a high current of approximately400 A/cm². The drain electrode 22 is made of nickel.

A plurality of trench grooves 110-112 are formed from the oppositesurface of the semiconductor substrate. A p⁺ gate region 13 is formed inthe semiconductor substrate along these grooves, and extendscontinuously to a position at which the p⁺ gate region 13 comes intocontact with the aforementioned source region 12. The gate region 13includes a p⁺⁺ draw-out layer 15 for forming a contact with a gatecontact layer 102. An aluminum-made gate electrode 103 is formed on thegate contact layer 102. A p-type field reduction region 16 is formed tosurround the p⁺⁺ gate draw-out layer 15. The field reduction region 16is not required when a breakdown voltage of interest is low. A channelstopper 17 is also formed outside the field reduction layer 16.

On the bottom of each of the trench grooves 110-112, a metal conductor(virtual gate electrode) 101 is formed, in accordance with the presentinvention, to be in ohmic contact with the p⁺⁺ draw-out layer 14 formedin the gate region 13. In this embodiment, the metal conductor (virtualgate electrode) 101 is made of a laminate film of titanium and aluminum.

Though insulated from the gate electrode 103 and external wiring, themetal conductors 101 are brought into ohmic contact with the gate region13 at locations deeper than the bottoms of the trench grooves 110-112,and therefore significantly reduce the gate resistance, as compared witha structure without the metal conductors 101. In this way, the metalconductors 101 can largely reduce the gate resistance, though atlocations deep in the gate region 13, and therefore produce a similareffect to that of a gate electrode, so that the metal conductors 101 canbe called the “virtual gate electrodes” in this sense.

In this way, it is possible to provide high-current JFET and SIT whichcan reduce the gate resistance to accomplish high speed switchingoperations.

The trench grooves 110-112 are embedded with an insulating film(insulating material) 31, and an interlayer insulating film (insulatingmaterial) 32 is disposed between respective source contacts 21 on thesurface of the semiconductor substrate.

FIG. 2 is a cross-sectional view generally illustrating the structure ofa static induced transistor (SIT) according to a second embodiment ofthe present invention.

In the present invention, a reduction in channel width is effective forenhancing the blocking effect of the gate, however, the channel need notbe reduced in width entirely in the depth direction of the channel. Forthis reason, the gate region 13 need not be formed over the entire sidewalls of the grooves. In the second embodiment, the gate region 13 isformed along the bottoms of the trench grooves 110-112 within a range inwhich the gate region 13 does not reach the source region 12 formedalong the opposite surface of the semiconductor substrates. The metalconductor (virtual electrode) 101 is formed on the bottom of each of thetrench grooves 110-112 for reducing the gate resistance, and an ohmiccontact is established between the p⁺⁺ gate draw-out layer 14 and eachmetal conductor 101. Thus, the resulting high-current semiconductordevice exhibits high-speed switching characteristics. The remainingstructure is similar to that illustrated in FIG. 1.

FIG. 3 is a cross-sectional view generally illustrating the structure ofa static induced transistor (SIT) according to a third embodiment of thepresent invention.

The structure in the third embodiment is substantially the same as thatillustrated in FIG. 2 except that the gate region 13 has a roundedcontour. In this embodiment, the resulting high-current semiconductordevice exhibits high-speed switching characteristics, as is the casewith the semiconductor device of the second embodiment illustrated inFIG. 2. The remaining structure is similar to that illustrated in FIG.1.

FIG. 4 is a cross-sectional view generally illustrating the structure ofa static induced transistor (SIT) according to a fourth embodiment ofthe present invention. The fourth embodiment differs from theembodiments illustrated in FIGS. 1 to 3 in that the trench grooves areembedded with an insulating film which is composed of a silicon oxidefilm 31 and a polysilicon film 33 in a two-region structure, and asource contact layer 21 is formed not only on the source region 12 butalso on the polysilicon film 33 which overlie the trench grooves.

When a contact hole is formed above the source region 12 after theinterlayer insulating film 32 has been formed, a dry etching or a wetetching method is used. In this event, when a silicon oxide film isformed above the trench grooves as in the first embodiment, the siliconoxide film within the trench grooves is also etched during the etching,possibly causing the gate region 13 to come into contact with the sourcecontact layer 21.

On the other hand, the polysilicon film 33, filled in the trench groovesas in the fourth embodiment, is not etched, so that the source contactlayer 21 can be formed not only on the source region 12 but also overthe trench grooves. This eliminates the need for taking intoconsideration a misalignment of the contact hole to the source region12, thus making it possible to achieve further scaling down.

FIG. 5 is a cross-sectional view generally illustrating the structure ofa static induced transistor (SIT) according to a fifth embodiment of thepresent invention. The fifth embodiment in FIG. 5 differs from thefourth embodiment in FIG. 4 in the way the silicon oxide film 31 andpolysilicon film 33 are embedded in the trench grooves. Anyway, thesefilms are embedded such that the polysilicon film 33 extends over theentire width of the trench grooves 110-112.

In the foregoing way of embedding the silicon oxide film 31 andpolysilicon film 33, a misalignment of the contact hole with the sourceregion 12 need not be taken into consideration, thus making it possibleto achieve further scaling down, as is the case with the fourthembodiment.

FIG. 6 is a cross-sectional view generally illustrating the structure ofa static induced transistor (SIT) according to a sixth embodiment of thepresent invention.

The sixth embodiment differs from the first embodiment illustrated inFIG. 1 in that the gate contact layer 102 and gate electrode 103 areformed on the bottom of one of the trench grooves. Specifically,assuming that the trench grooves 110, 111, identical to those in FIG. 1,are designated first grooves, a second p-type gate region 131 is alsoformed along a second trench groove 113. Then, the gate contact layer102 and gate electrode 103 are formed on the bottom of the second trenchgroove 113 in opposition to a draw-out layer 151 in the second p-typegate region 131.

Likewise, in the sixth embodiment, since the on-resistance is lower asthe channel width is narrower, the gate resistance is preferably reducedas well in the first gate region 13 within the region in which thesource electrode 23 is formed. To meet this requirement, the metalconductor (virtual gate electrode) 101 is formed on the bottom of eachof the trench grooves 110, 111 independently of the gate contact layer102 and gate electrode 103, thereby reducing the gate resistance toenable high-speed switching operations.

FIG. 7 is a cross-sectional view generally illustrating the structure ofa static induced transistor (SIT) according to a seventh embodiment ofthe present invention.

A difference between the seventh embodiment and the sixth embodimentillustrated in FIG. 6 is the same as the difference between the firstembodiment in FIG. 1 and the fifth embodiment in FIG. 5. Specifically,the silicon oxide film 31 and polysilicon film 33 are embedded in thetrench grooves 110-112 such that the polysilicon film 33 extends overthe entire width of the trench grooves 110-112, thereby eliminating theneed for taking into consideration a misalignment of the contact hole tothe source region 12 to achieve further scaling down.

FIG. 8 is a top plan view illustrating the layout of a mask pattern forimplementing the first embodiment of the present invention. The layoutincludes a mask pattern 801 for a source contact layer, and a maskpattern 802 for a gate contact layer, with which the semiconductorsubstrate is processed such that contact regions are left withinrespective rectangles defined thereby. A mask pattern 803 for a gatedraw-out layer is intended to inject ions within a rectangle definedthereby. A mask pattern 804 for an n-type source region is intended toinject ions within a rectangle defined thereby. A mask pattern 805 fortrench grooves is intended to form grooves within a rectangle definedthereby. In this embodiment, after forming the mask pattern 804 for ann-type source region, grooves are formed using the mask pattern 805 fortrench grooves. A mask pattern 806 for making a contact hole forconnecting the gate draw-out layer 15 to the gate contact layer 102,shown in FIG. 1, is intended to make a contact hole within a rectangledefined thereby. A mask pattern 807 for making a contact hole forconnecting the source region 12 to the source contact layer 21, shown inFIG. 1, is intended to make a contact hole within a rectangle definedthereby.

FIG. 9 is a top plan view illustrating the layout of another maskpattern for implementing the first embodiment of the present invention.When the source contact layer mask pattern 801 is surrounded by the gatecontact layer mask pattern 802, a two-layered contact region is requiredfor intersecting the source contact layer 21 with the gate contact layer102. However, a further reduction can be achieved in the gateresistance.

The mask patterns illustrated in FIGS. 8 and 9 are unit cells, and ahigh-current device is created by arranging a large number of these unitcells in the vertical and horizontal directions.

FIGS. 10A to 10I are cross-sectional views illustrating the structure ofthe SIT in manufacturing steps A-I for manufacturing the SIT accordingto the first embodiment of the present invention. As illustrated in FIG.10A, a photo-resist 401 is coated on an n⁺ substrate 10 and an n-type4H-SiC base which includes an epi-layer 11, for example, having athickness of 6 μm and a concentration of 2E16/cm⁻³, and is processed indesired regions. Subsequently, n-type impurity ions 402 such as nitrogenions, phosphor ions or the like are injected to form n-type regions 12,17. Then, the photo-resist is removed, and a silicon oxide film 403 isdeposited, for example, by a CVD (Chemical Vapor Deposition) method orthe like, as shown in FIG. 10B, and processed into a desired shape usingthe photo-resist 401 and the like as a mask. Subsequently, trenchgrooves of 1.2 μm depth are formed in the SiC base, as shown in FIG.10B, using the silicon oxide film 403 as a mask.

Next, as shown in FIG. 10C, p-type impurity ions 404, for example,aluminum ions, boron ions or the like are injected into the base once toseveral times with an inclination of several degrees to several tens ofdegrees to the base and with energy ranging from several tens to severalhundreds of keV to form a p-type region 13. Also, p-type impurity ions404, for example, aluminum ions, a boron ions or the like areperpendicularly injected into the base once to several times with energyranging from several tens to several hundreds of keV to form a draw-outlayer 14 within the p-type gate region 13. Here, as illustrated in FIG.10D, the silicon oxide film 403 and the like are all removed, and theresulting base is annealed, for example, in an argon atmosphere torecover from defects caused by the ion injection.

Next, as illustrated in FIG. 10E, a metal, for example, nickel or thelike is vapor deposited over the semiconductor substrate to form a drainelectrode 22. Also, a photo-resist 401 is coated on the base andprocessed to remove desired regions. Subsequently, as illustrated inFIG. 10E, a metal, for example, a laminate film made of titanium andaluminum, a single film of nickel or the like is vapor deposited to formthe foundation of a metal conductor (virtual gate electrode) 101according to the present invention.

Here, the resist 401 is removed, as shown in FIG. 10F.

Next, as illustrated in FIG. 10G, an insulating material (insulatingfilm) 31 such as a silicon oxide film, a polysilicon film or the like isembedded to planarize the opposite surface of the base. Now, asillustrated in FIG. 10H, an interlayer insulating material (insulatingfilm) 32 such as a silicon oxide film is deposited by a CVD method orthe like, and is processed in desired regions by a photolithographicstep and a wet etching method or the like. Next, as illustrated in FIG.10I, a source contact layer 21 and a gate contact layer 102, both madeof a nickel film or the like, are deposited on the surface of the SiCbase which is then annealed at temperatures ranging from severalhundreds to several thousands of degrees to form a silicon/metalreaction region between the metal film and the SiC substrate. Then, ametal film made of aluminum or the like is deposited to form a sourceelectrode 23 and a gate electrode 103, and the resulting product isannealed at temperatures of several hundreds of degrees, resulting inthe completion of the SIT according to the first embodiment asillustrated in FIG. 1.

According to the foregoing embodiment, since the semiconductor devicecan accomplish a low gate reverse bias and a low on-resistance, thesemiconductor device, when used as a switching device for an PWMinverter, can advantageously facilitate gate driving and reduce a loss.

It should be further understood by those skilled in the art thatalthough the foregoing description has been made on embodiments of theinvention, the invention is not limited thereto and various changes andmodifications may be made without departing from the spirit of theinvention and the scope of the appended claims.

1-15. (canceled)
 16. A silicon carbide semiconductor device having avertical field effect transistor, said field effect transistorcomprising: a substrate of a first conductivity type having a lowconcentration of impurity, said substrate constituting a semiconductorsubstrate, the band gap of which is 2.0 eV or more; a drain electrodeformed over one surface of said substrate; an epitaxial layer of thefirst conductivity type formed on an opposite surface of said substrateand having a lower resistance than said substrate; a source region ofthe first conductivity type formed along the opposite surface of saidsemiconductor substrate; a plurality of first grooves formed from theopposite surface of said semiconductor substrate; a first gate region ofa second conductivity type formed along said first grooves; a sourcecontact layer formed on an opposite surface side of said source region;a source electrode in ohmic contact with said source contact layer; asecond groove formed from the opposite surface of said semiconductorsubstrate; a second gate region of the second conductivity type formedalong said second groove; a gate electrode in ohmic contact with adraw-out layer in said second gate region through a gate contact layer;and a metal conductor in ohmic contact with a contact layer in said gateregion on the bottom of each said first groove independently of saidgate electrode.
 17. A silicon carbide semiconductor device according toclaim 16, wherein said metal conductor is electrically isolated fromsaid gate electrode.
 18. A silicon carbide semiconductor deviceaccording to claim 16, wherein said metal conductor is electricallyisolated from a wire from the outside.
 19. A silicon carbidesemiconductor device according to claim 16, wherein said gate regionformed along said first grooves is formed to be in contact with saidsource region formed along the opposite surface of said semiconductorsubstrate.
 20. (canceled)